Example FIG. 1 is a cross-sectional view illustrating the implantation of N-type dopants according to a method for manufacturing a flash memory device. As shown in example FIG. 1, a flash memory device includes a stack gate pattern, which includes a tunnel oxide layer 110, a floating gate 120, ONO layers 131, 132, and 133 and a control gate 140 on the silicon substrate 100. In order to form a spacer on the stack gate pattern, a lower spacer oxide layer 151, a spacer nitride layer 152, and an upper spacer oxide layer 153 are sequentially deposited using a CVD (Chemical Vapor Deposition) method. Thereafter, if a dry etching process is executed to form the spacer, a spacer structure may be formed at both sides of the stack gate pattern as shown in example FIG. 1.
However, the higher the memory capacity, the higher the integration degree of the flash memory device should be, such that the spacer thickness is unavoidably limited. As the integration degree of the flash memory device increases (i.e., feature size decreases), the flash memory device becomes weaker in the important characteristics (e.g., data retention fail (DRF) and high temperature operating life (HTOL)) associated with performances of the flash memory device. Particularly, the smaller the device size, the thinner the spacer which contributes to the loss of data. Indeed, the aforementioned data-loss problem is considered to be a serious problem in flash memory devices where the line width is 13 nm or less. To make matters worse, if the contact hole further limits the thickness of the spacer, the aforementioned data-loss problem caused by the spacer becomes more serious.
Therefore, as the spacer becomes thinner by shrinking a flash memory device, the stored data may be more easily lost, thereby reducing the reliability of the flash memory device.